Forum Discussion

SAbde7's avatar
SAbde7
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

How to fully constrain a design with several synchronous clock domains?

My design only has one clock. I use a cyclic shift register containing only a single 1 to generate enable signals used to divide the Frequency. I use a 4 bit shift register to create 4 enables out o...
KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

Hi,

You may refer to AN 433: Constraining and Analyzing Source-Synchronous Interfaces https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an433.pdf for constraining the source synchronous interface.

You have to apply:

  • Clock constraints: Describe the required times for data to be valid at the interface
  • Input or output delay constraints; either in System-centric method or FPGA-centric method: Describe the required times for data to be valid at the interface.
  • Timing exceptions: Control launch and latch edges used in timing analysis. Timing exceptions ensure that valid timing paths in the interface are analyzed, and invalid paths are not analyzed.

Please let me know if you have any questions.

Thanks.