Forum Discussion
New ContributorHow to fix "Warning (10030): Net "microcode1.data_a" at MAX10CPU.sv(10) has no driver or initial val
You can use synthesis attributes: https://www.intel.com/content/www/us/en/programmable/quartushelp/17.0/hdl/vlog/vlog_file_dir_ram_init.htm
Super ContributorYes, that's another way to do it with the memory as an IP and a .hex or .mif file. It seemed like you wanted to do it through code inference.
New ContributorIf there's another way to do this, I love to hear about it.
I didn't really understand your previous comment about using a .dat file. The .mem file I'm using is in the format accepted by $readmemh.
- sstrell
I've always used .dat for this. I've never actually heard of .mem. This article uses .txt actually: https://fpgacoding.com/test-bench-data-files-in-verilog/
- BobA
It's just the extension. I know the file's contents are in $readmemh's format.
The bigger concern is that the 'initial' block doesn't get synthesized. But is there another way to initialize memory in the synthesized Verilog?
