How to fix timing issues using the timing assignment options?

In your PLL you should create 4 output clocks with phase shift of 0, 90, 180 and 270 degree. Do not use an inversion of 0 and 90 to get 180 and 270.

Remeber you will pass an additional delay using an inverter, and you relie on 50% duty cycle clock.

The advantage in having 4 outputs from the PLL is also that you can fine-tune the delay to take account of different routing on the PCB.

The ad8200 is not spec'd (guranteed) at more than 200MS/s, so a product requiring 250MS/s is kind of risky.

Rember you wont get an analogue bandwidth anywhere near nyquist of 500MHz unless you preceed your circuit with S/H.