How to fix timing issues using the timing assignment options?

Thanks so much for all your concern.

It's a product. A 1GHz sample rate digital oscillograph.I'm using the four clocks at 250MHz for sampling which 90 degree phase shift each other. The data capturing clock is also 250MHz,this four are the same 90 degree phase shift each other.I'll attach a file to describe my design.

ALL the interfaces IO standard using are LVTTL. In my design, I change the four phase 250MHz data flow into 125MHz data flow,using the "SinPout" module attached above,then I capture the four phase 125MHz data flow at a appropriate time to ensure the setup and hold relationship correctly,after that,the 125MHz data flow is aligned, so I store the data into a RAM. The data stored can be accessed by a DSP chip.

By the way, I choose those devices with a cost consideration. In the device handbook,it shows under -8 speed,input clock rate are both 387MHz for row pins and column pins.the clock tree fmax is 275MHz.So I consider it can receive 250MHz data flow.

But now,I'm encountering bad timing issue about storage.Indeed,the timing requirement is so tight.AD's output has a just 2ns hold time.Please give me suggestion about timing constraints.

Thank you.