How to fix timing issues using the timing assignment options?

I'm slightly confused in the implementation. Are you doing 1GHz data and then capturing it with four phases of the PLL, all at 250MHz?

Note that you're in the slowest speed grade of a low cost family, two generations old(CIII is shipping), doing a high-speed interface. (I'm not sure what IO standard you're using). 250MHz is going to be exremely hard to meet(if you're trying to capture 1GHz data, it won't work). You're Tsu/Th constraints are going to be extremely tight, and make sure you run them on both timing models(Assignments -> Settings -> Classic Timing Analyzer -> More Settings -> Run Combined Fast/Slow Models) There's a chance you won't be able to meet your constraints.

You probably want to do SPICE simulations of your board. You're not in a wire-bonded package, so you're IO characteristics are not going to be nearly the quality of new packages(they are more expensive and harder to use, but they have a lot of good qualities).

Naturally, I'm not familiar with your situation, but just voicing some concerns. Is this a product or just trying to get something to work?