How to fix timing issues using the timing assignment options?

Your design looks ok to me, as a starter though, because you need some way to synchronize this block with the other 4. As it is drawn, you have now way of knowing if sample N ends up as a high byte or low byte in your output port. So you need a sync input to your feq-div2 block.

Obviously you still need some way of absorbing the phase difference between your 4 adc clocks. This block only halves your effective clock rate.

Constraining the timing should not involve multicycle here. In fact this block is a standard single clock synchronous block what timing concerns. Its the next block which presumably will bring you clock down to 125MHz which will benefit from multi-cycle constraining.

Personally I would probably (try to) use a dual clock fifo for this, as I mentioned previously, because this would be able to deal with both your phase matching problem as well as halving the clock rate (set fifo.we=DFFE.ena and fifo.wRclk=ClkShift1, fifo.re=Vcc, fifo.rclk=CLK125MHz). Ofcourse the fifo need to be fast enough to do this trick, not sure it is in fact.

Rysc is right at pointing out the problem with matching up the delay, but this problem is there no matter what you do and will require careful design and simulation.

By the way this is an interesting project. Did you see this thread?

http://www.alteraforum.com/forum/showthread.php?t=260&highlight=adc (http://www.alteraforum.com/forum/showthread.php?t=260&highlight=adc)

Can you tell us if and how you plan to match the response in the 4 channels? I here speak in terms of response from analogue input signal to the 4 digital interleaved outputs.