How to fix timing issues using the timing assignment options?

Thanks very much,all of you.

I will make a practice on my design as you mentioned.Let QII satisfy timing performance through assignment. If there is something can't be solved myself, I will turn to your help again.

Actually,my project is data acquisition system of digital storage oscillograph. Using the four 90 phase shift clock to get 1GHz sample rate. I don't use a FIFO or RAM to directly receive the 250MHz data flow, because,FPGA used is -8 speed grade.I need first make data align. After the data is phase aligned,then stored in a RAM.

I will attach my design about 250MHz data flow receiver.Please give me some suggestion.

Thanks.

Have a nice day.