How to fix timing issues using the timing assignment options?

I believe you're doing a phase-comp FIFO. (It's almost easier to build your own, since you generally don't need any sort of hand-shaking or empty/full flags, just free-running clocks. I can post one I wrote two weeks ago if you're interested). The other thing is phase-comp FIFOs have a variable delay, since you don't know whether the read or write clock will occur first. So if you have a phase-comp fifo for each A/D, it will be difficult to match up all the data. PC-FIFOs work best when the clocks are 0PPM difference(this is a requirement) but you have no idea what their phase relationship is.

I don't think that will help in that case as the problem is writing the data in, and they'd still have to meet timing requirements when writing into th PC FIFO. If you don't have correct timing analysis between the data and the write clock, you'll potentiall write different bits of data into different clock cycles, as well as introduce metastability.