How to fix timing issues using the timing assignment options?

Inserting cells in order to adjust the delay is an unrelaible way to solve your IO timing problems. Problem is that you also depend on the routing and speed grade of your device. So you may end up having a design which does not work after a simple recompile because of changed routing, and not to mention the impact of a change of speed-grade during production.

Instead put a dual clock fifo in you data path. This will give you a clean design where you can solve your timing issues by adjusting the IO clock without concern of the data reception timing in the downstream path which runs on another clock but at its own phase. You need a small state-machine to fill your fifo with a few data lines after the reset.