How to fix timing issues using the timing assignment options?

frsustrated is right, in that you need to enter correct IO constraints first. You mention that you're "adjusting the storage clock's dealy to satisfy data valide period and prevent the transiting data being stored." You also need to tell Quartus what requirements it needs to meet. I would stay away from inserting LCELL buffers, as that is much too coarse grained of a solution. The fitter can make use of placement, routing, and the input delay chain to meet your timing, so it generally does a much better job than manual work. If you want to mess with anything, there is the Input Delay Chain, which I believe is 0-3 in Cyclone, which you can make assignments for and control post-fit in the chip editor. But Quartus should be properly setting these to meet your timing constraints.

Now, if the interface still fails when it meets your timing constraints, you'll have to do some debugging as to why the constraints are incorrect. There's some methodology there(lock down the register and tweak the data path or the PLL shift until it starts working to see where the window is), but you usually this is just a sign of having entered incorrect constraints.