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AChri1's avatar
AChri1
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7 years ago

How to fix DDR2 memory in MAX10 giving error 17044 when compiling.

I get the following : Error (17044): Illegal connection on I/O input buffer primitive max10_test_ddr3:inst|max10_test_ddr3_mem_if_ddr2_emif_0:mem_if_ddr2_emif_0|max10_test_ddr3_mem_if_ddr2_emif_0_p0:p0|max10_test_ddr3_mem_if_ddr2_emif_0_p0_memphy_m10:umemphy|max10_test_ddr3_mem_if_ddr2_emif_0_p0_addr_cmd_pads_m10:uaddr_cmd_pads|altera_gpio_lite:clock_gen[0].umem_ck_pad|altgpio_one_bit:gpio_one_bit.i_loop[0].altgpio_bit_i|diff_input_buf.diff_input_buf_without_nsleep.ibuf. Source I/O pin max10_test_ddr3:inst|max10_test_ddr3_mem_if_ddr2_emif_0:mem_if_ddr2_emif_0|max10_test_ddr3_mem_if_ddr2_emif_0_p0:p0|max10_test_ddr3_mem_if_ddr2_emif_0_p0_memphy_m10:umemphy|max10_test_ddr3_mem_if_ddr2_emif_0_p0_addr_cmd_pads_m10:uaddr_cmd_pads|altera_gpio_lite:clock_gen[0].umem_ck_pad|altgpio_one_bit:gpio_one_bit.i_loop[0].altgpio_bit_i|pseudo_diff_output_buf.obuf_a drives out to destinations other than the specified I/O input buffer primitive. Modify your design so the specified source I/O pin drives only the specified I/O input buffer primitive.

When compiling and not setting setting the .qip file to top level.

I have a .gdf file as top level. I am trying to connect ddr2 memory to an external 32 bit processor via a multiplexed 32bit data/address bus and implement ECC in the MAX10.

Any suggestions?

3 Replies

  • BoonT_Intel's avatar
    BoonT_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    7 years ago

    Hi,

    If you are not setting the IP QIP file as top level. Then you need to connect all memory interface signal (ADD/CMD and DQ/DQS) to your top level file. the IP will require you to connect all interface pin to physical I/O to pass fitter.

  • Abe's avatar
    Abe
    Icon for Frequent Contributor rankFrequent Contributor
    7 years ago

    After you instantiate the DDR2 controller via Qsys, did you run the pin placer TCL script? Please search the project folders for a pin_assignment.tcl TCL script and run it. It will help place the DDR IO pins and resolve such issues.

  • BoonT_Intel's avatar
    BoonT_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    7 years ago

    Hi Abe,

    Thanks for your help.

    For DDR IP, it only provide pin assignment tcl which help to assign IO setting like IO standard. However, there is not pin placer TCL.

    User need to assign location by them self or let Quartus auto fit and run back annotate to lock the location.