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JoEl's avatar
JoEl
Icon for Occasional Contributor rankOccasional Contributor
6 years ago
Solved

How to fill Platform designer documentation

Hi all, I am looking for some source code documentation tool like doxygen for SystemVerilog with no luck, but I find that Quartus can generate nice HTML block design. How can I insert code in it ? I...
  • KennyT_altera's avatar
    KennyT_altera
    6 years ago

    Hi Josef,

    The enhancement is for our engineering. Currently, they are no parameter that you can use for hw.tcl or setting files for this generation.

    Thanks

JoEl's avatar
JoEl
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

Hi Kenny,

I saw all your links before excluding ftp you send, but nor of those speaks about what fills html file generated with core. I want description like what I need to set wher to propagate to those HTML.

I know how user IPs are made, how to modify them...

we do use own repository with component root file, with component_hw.tcl in it, and simulation, hdl and documentation folders.

When quartus do compilation, in structure described above quartus provide html file (easy readable) but there isn't enougth information. But Intel cores are described there better. So what I want is guide what I need to propagate my toughs to HTML not how to do IP

Best regards, Josef