How to fill Platform designer documentation
Hi all,
I am looking for some source code documentation tool like doxygen for SystemVerilog with no luck, but I find that Quartus can generate nice HTML block design. How can I insert code in it ? I cannot find any reference about it. Is it same like description in IP library? - I don't know how to do that neither but interested in it.
When you open top level project folder, with qsys in it (we have top level entity as wrapper for QSYS now) you have folder named same as your top level QSYS. See pic below and it contain information about qsys components like parameters, sw dependencies, connection, base addresses... Question is how to set those parameters cause this documentation looks usable...
If anybody can point me to some document about it I would be appreciated.
Thanks, Joe
Hi Josef,
The enhancement is for our engineering. Currently, they are no parameter that you can use for hw.tcl or setting files for this generation.
Thanks