New Contributor
New ContributorHi,
when we experience similar problems, it often turns out to be incorrect timing constraints. But you are already investigating this. You could also focus on power issues. Once we encountered similar problems on Arria10, when we added computationally expensive feature. Sometime it worked sometime it did not. It turned out, that as chips heated, their power consumption increased and the power source was not good enough. The better cooling solved the issue. So I would recommend to investigate temperature/power quality.
Jan
New ContributorJan,
Thank you for the reply. As you say large designs do require more power and we are checking into that as a possible cause. It is in our pipeline to get a power source that supports higher current to see whether it makes a difference. As it is we don't see dips in the core voltage when we put a scope on it. And the temperature of the part does not measure as excessive. We do have heat sinks.
Regards,
John
New ContributorHi,
I see you write several time about Core voltage but you describe trouble with I/O interfaces. Did you check also other voltage rails (transceivers can behave weird if the voltage is not correct, particularly during their calibration and reconfiguration)?
Jan
New ContributorHi Jan,
Yes, we are investigating that as well.
At this time we have opened an internal investigation with Intel so not all of our findings will be on this public forum.
Thank you for your interest.
John
