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Altera_Forum's avatar
Altera_Forum
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17 years ago

How to dump the netlist in Verilog for reading the implementation done by Quartus

I just want to know ppl that is there a way by which we can see the compiled and synthesized netlist, I have come across only the netlist viewer tool in GUI which when I open in resource editor I can...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

One option is to enable the *.vho netlist output for ModelSim gate level simulation. It gives a flat VHDL-like netlist.