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So how can I know whether design meets timing? Through timing analysis?
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Yes. Static timing analysis using TimeQuest. Creating the .SDC constraints file is sometimes an iterative process, where you first identify the obvious (external) clocks, and then add PLL constraints, I/O setup and hold constraints, cut timing paths of the inputs and outputs you don't really care about (LEDs, push-buttons, asynchronous signals, etc), until all clocks and I/Os are constrained. You can place-and-route the design between iterations, or just use the TimeQuest GUI, and delete the netlist and re-read the .SDC file until you clear as many warnings as you see fit. Then place-and-route the design with the final .SDC file.
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Sometimes after I finish completed compilation, there is critical warning that indicates the design does not meet timing requirements, but I don't know how to handle it.
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You look at the path of the timing violation. If its your code, then you look at the design and try to think of a way to change it. For example, can a pipeline stage be added to a long combinatorial path? Or perhaps a N clock multi-cycle constaint can be applied to a particularly long data path, and a control state machine added to enable the path every N clock cycles.
Its a bit trickier when it comes to a timing violation in Altera-provided IP. In that case, you're better off to create a small design that shows the timing error, and then submit a service request to Altera, and ask for their recommendation. I have exactly this issue with the PCIe core in the Cyclone IV GX device.
Cheers,
Dave
Honored Contributor
