Forum Discussion
4 Replies
- RichardT_altera
Super Contributor
You may checkout this user guide for how to simulate using Questa*-Intel® FPGA Edition, with the example design provided in the document.
https://www.intel.com/content/www/us/en/docs/programmable/691278/21-3/quick-start.html
Regards,
Richard Tan
- RichardT_altera
Super Contributor
Hi,
Dropping a note to ask if my last reply was helpful to you?
Do you need any further assistance from my side?
Regards,
Richard Tan
- Amit4
New Contributor
Hi Richard,
Thank you for your reply. The issue is resolved now.
However, I have different problems related to implementing the jesd204 design example and doing FPGA implementation. I have generated the design example; for FPGA implementation, I am using Altera Apollo SOM board and AFE79xx EVM; I need help with the pin assignment, like how to check which pins to give for refclk_core and refclk_xcvr and mgmt_clk, etc.
Can you please help me with this?
Thank you
Regards
- RichardT_altera
Super Contributor
I'm pleased to hear that your question has been addressed.
At Altera, we recommend opening a new case for each unique technical issue. This helps with case analysis and allows us to better assess your support needs.
I noticed you've submitted a follow-up question in a new case, and an agent will be assigned to it shortly.
You can follow your case here:
Pin Assignment for JESD204B using Apollo Agilex 7 and AFE79 EVM
Now, I will transitioning this thread to community support. If you have any further questions or concerns, please don't hesitate to reach out. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support.
The community users will be able to help you on your follow-up questions.
Thank you and have a great day!
Best Regards,
Richard Tan