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Altera_Forum
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Honored ContributorHow to develop a verilog model for a Peak detector with various constraints
Develop a Verilog Code for a Peak detector the following functions:
Note: A threshold value is assigned to the sample ( noise barrier)- Finds the Maximum peak from a sample of 24 bits when the pulse goes above the threshold.
- Counter stores value when pulse goes over threshold.
- If during a sample there are two or more pulses combined to one-another each peak and counter values are to be saved.
- Counter stores value when pulse goes to threshold. counter calculates pulse width.
- Each sample arrives during clock cycles when data_in =1.
- All peak and pulse width values are sent to a FIFO.
3 Replies
Altera_ForumWhat do you want us to tell you, apart from the bad syntax of your code, which you could have discovered from trying to compile it.
- Altera_Forum--- Quote Start --- What do you want us to tell you, apart from the bad syntax of your code, which you could have discovered from trying to compile it. --- Quote End --- I am new to Verilog and i dont really know much about the syntax, I hoping for someone to help me clean up the code so i can use that as a basis to learn the verilog syntax. Thanks.
- Altera_Forum
Much better to find a good Verilog Text book or use google for a tutorial - there are many of these to help yourself with.
