How to develop a verilog model for a Peak detector with various constraints

Develop a Verilog Code for a Peak detector the following functions:

1. Finds the Maximum peak from a sample of 24 bits when the pulse goes above the threshold.

2. Counter stores value when pulse goes over threshold.

3. If during a sample there are two or more pulses combined to one-another each peak and counter values are to be saved.

4. Counter stores value when pulse goes to threshold. counter calculates pulse width.

5. Each sample arrives during clock cycles when data_in =1.

6. All peak and pulse width values are sent to a FIFO.