How to determine signal's width dynamically in VHDL, a stupid question?

Hello David,

I don't think it's a stupid question. I wonder, why most VHDL guides never touch it.

Personally, I have often used a construct like this

USE ieee.math_real.log2;
USE ieee.math_real.ceil;
...
CONSTANT NBIT	: INTEGER := INTEGER(CEIL(LOG2(REAL(MAXCOUNT-1)));

Alternatively, you can use an integer log2 function, like this

function log2(A: integer) return integer is
begin
  for I in 1 to 30 loop  -- Works for up to 32 bit integers
    if(2**I > A) then return(I-1);  end if;
  end loop;
  return(30);
end;

If the bitcount constant shall be used in the entities generic part, it must be supplied by another module or a package preceeding the entity definition. If it is needed in the architecture declaration only, all calculations can be done here.

Best regards and Happy New Year!

Frank