Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

How to deal with on chip memory timing?

I want to make a fsm on an altera FPGA which uses on-chip memory. I want to take an input, get data from memory based on input, use that data in the next cycle. and so on. What is a good way to ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

There's no special advice, just follow the HDL guidelines for RAM inferral.

The on-chip RAM blocks are capable of operating at the chip's maximum clock frequency, so they're very unlikely to be the bottleneck in your design.