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NuvKFC's avatar
NuvKFC
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5 years ago
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How to deal with glitch free clock switch when use auto gated clock conversion?

I get an ASIC design which contains many glitch free clock switch as follows picture. When I use auto gated clock conversion option, tool said that it's an unsupported cascaded clock so that tool can't convert it.

Could someone have the experience to share with me? Thank you very much.

5 Replies

  • NuvKFC's avatar
    NuvKFC
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    5 years ago

    Whether someone has the experience to share please? Thank you very much.

  • SyafieqS's avatar
    SyafieqS
    Icon for Super Contributor rankSuper Contributor
    5 years ago

    Hi KFc,


    What device are you using for ASIC prototyping?

    Auto Gated Clock Conversion logic option only available Arria series, Cyclone II, Cyclone III, Cyclone IV, HardCopy series, Stratix II, Stratix II GX, Stratix III, Stratix IV, and Stratix V) families. You need to double check this.


    • NuvKFC's avatar
      NuvKFC
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      4 years ago

      Hi SyafieqS_Intel

      Thank you, SyafieqS_Intel, very much. I'm using Stratix IV. But tool said that it's an unsupported cascaded clock so that tool can't convert it.

    • NuvKFC's avatar
      NuvKFC
      Icon for Contributor rankContributor
      4 years ago

      Hi SyafieqS_Intel

      Thank you very much.