Forum Discussion

NuvKFC's avatar
NuvKFC
Icon for Contributor rankContributor
4 years ago
Solved

How to deal with glitch free clock switch when use auto gated clock conversion?

I get an ASIC design which contains many glitch free clock switch as follows picture. When I use auto gated clock conversion option, tool said that it's an unsupported cascaded clock so that tool can...
SyafieqS's avatar
SyafieqS
Icon for Super Contributor rankSuper Contributor
4 years ago

Hi KFc,


What device are you using for ASIC prototyping?

Auto Gated Clock Conversion logic option only available Arria series, Cyclone II, Cyclone III, Cyclone IV, HardCopy series, Stratix II, Stratix II GX, Stratix III, Stratix IV, and Stratix V) families. You need to double check this.


  • NuvKFC's avatar
    NuvKFC
    Icon for Contributor rankContributor
    4 years ago

    Hi SyafieqS_Intel

    Thank you, SyafieqS_Intel, very much. I'm using Stratix IV. But tool said that it's an unsupported cascaded clock so that tool can't convert it.