How to create delay cell

My Question is Why?

using logic to create clocks is never going to be very stable or reliable as they are affected alot by P&R and PVT. So even when you lock the logic to specific cells you will still get variations in the output frequency and skew.

The after command is a simulation only contruct. To put in a delay cell you will have to manually instantiate a cell, and then ensure the synthesis does not optimise the design. And then you will probably need to place it manually to tweak the correct frequency. This could be rather time consuming, and will then probably be affected if you change the design as the routing resources are changed.

Altera provides the LCELL Primitive for this function: http://quartushelp.altera.com/15.0/mergedprojects/hdl/prim/prim_file_lcell.htm

But you could save yourself all the pain by just using a PLL and setting the multiplier to x2