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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

How to correct the error

LIBRARY ieee;

USE ieee.std_logic_1164.all;

ENTITY CHAR_7SEG IS

PORT ( c : IN STD_LOGIC_VECTOR(2 DOWNTO 0);

HEX0 : OUT STD_LOGIC_VECTOR(0 TO 6));

END CHAR_7SEG;

ARCHITECTURE behaviour4 OF CHAR_7SEG IS

BEGIN

case c is

WHEN 000 =>

HEX0 <="76" ;

WHEN 001 =>

HEX0 <= "79";

WHEN 010=>

HEX0 <= "38";

WHEN 011=>

HEX0 <= "38";

WHEN 100=>

HEX0 <= "3F";

WHEN OTHERS =>

HEX0 <= "00";

END case;

END behaviour4; THE ERROR SHOWING IS ---->> Error (10500): VHDL syntax error at CHAR_7SEG.vhd(22) near text "case"; expecting ";", or an identifier ("case" is a reserved keyword), or "architecture" . HOW TO CORRECT THIS ERROR??

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    Outside a process you can write : 

    
WITH c SELECT
    HEX <= "01110110" when "000",
               "01111001" when "001",
              ....
               "00000000" when others;


    
WITH c SELECT
    HEX <= x"76" when "000",
               x"79" when "001",
              ....
               x"00" when others;

    But be aware that you are writing a MUX. It produces glitches.