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Well, I discovered, that at some registers my reset is used as "
clk enable", see attachment.
I suppose, the tool did that, because the data comes from a register clocked with 83 MHz to aregister clocked with 50 MHz. (I synchronize the data coming from the 83 MHz part with two 50 MHz registers, before using it.)
So, any ideas how I have to constrain
rstsync2?
Thanks for your support!
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That still does not explain the warning. see if you have connected rstSync2 to clock through some logic.
Regarding timing constraint, you don't need any for 1st reset section. The path from reset pin to rstSync1 register is not going to be checked because it is not between two registers and a false statement there is useless. The path after rstSync2 is now known to tool and it will check it. The path between rstSync1 & rstSync2 need a false statement.
As a side note, the reset vhdl code above does not implement a circuit according to diagram per your link, though I think it is equivalent. I believe that circuit is realisable only by instantiating a flip and not coding.
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