how to constraint the reset signal？

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If looking at VHDL doesn't help, try looking at the RTL netlist and see where rstSync2 is connected to a flip-flop's clock pin.

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Well, I discovered, that at some registers my reset is used as "clk enable", see attachment.

I suppose, the tool did that, because the data comes from a register clocked with 83 MHz to aregister clocked with 50 MHz. (I synchronize the data coming from the 83 MHz part with two 50 MHz registers, before using it.)

So, any ideas how I have to constrain rstsync2?

Thanks for your support!