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Altera_Forum's avatar
Altera_Forum
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17 years ago

how to constraint the reset signal？

i have designed my reset signal like following： http://www.logicpower.cn/articles/SOPC_timequest.files/image012.jpg so, i constraint reset_n signal like this: set_false_path -from [get...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

If looking at VHDL doesn't help, try looking at the RTL netlist and see where rstSync2 is connected to a flip-flop's clock pin.