how to constraint the reset signal？

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I have synchronized my asynchronous power on reset.

(It is described on the following site.)

-- Reset einsynchronisieren und zugleich invertieren
process (TiClkout50_i, PowerResetn_i)    
begin
    if PowerResetn_i = '0' then
        rstSync <= '1';
        rstSync2 <= '1';
    elsif rising_edge(TiClkout50_i) then
        rstSync <= '0';
        rstSync2 <= rstSync;
    end if;    
end process;
PowerReset <= rstSync2;

Timequest is complaining that it is a clock:

does anybody know how to constrain the generated reset?

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It must be you are (some where) using it as clock in a process edge rather than reset.