how to constraint the reset signal？

I have synchronized my asynchronous power on reset.

(It is described on the following site.)

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quartushelp.altera.com/12.1/master.htm#mergedProjects/verify/da/comp_file_rules_reset_external.htm?GSA_pos=7&WT.oss_r=1&WT.oss=syncronizing%20asynchronous%20reset

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-- Reset einsynchronisieren und zugleich invertieren
process (TiClkout50_i, PowerResetn_i)    
begin
    if PowerResetn_i = '0' then
        rstSync <= '1';
        rstSync2 <= '1';
    elsif rising_edge(TiClkout50_i) then
        rstSync <= '0';
        rstSync2 <= rstSync;
    end if;    
end process;
PowerReset <= rstSync2;

Timequest is complaining that it is a clock:

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Warning: Node: TopFpga:TopFpga_inst|rstSync2 was determined to be a clock but was found without an associated clock assignment.

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does anybody know how to constrain the generated reset?