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Altera_Forum's avatar
Altera_Forum
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17 years ago

how to constraint the gated clock in the Timequest？

i need to use gated clock in my design, and like following: module prac ( a, b, rst_n, out ); input a; input b; input rst_n; ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

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O.K. can you tell about the expected a and b timing? Of course, if minimum H and L pulse widths are guaranteed for (a && b), there's probably no problem

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when a && b == 1, it will keep at least two period---40ns, and a && b == 0,it will keep at least 10us.

and a,b maybe flip high at the same time, that is uncertain.