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The behaviour is different, also without timing violations, cause it's an AND operation. So I don't know, if you intend the above coded or the descripted behaviour.
If
a and
b aren't too fast, synchronous processing based on sufficient fast system clock would be my favourite solution. Of course, an exact behavioural specification, also considering possible overlappping of both signals, must exist.
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i am sorry ,
a and
b is as fast as the system clock of my design, 50MHz, and even if
a and
b delay a period--20ns, this will be cause a control mistake, so i didn't know how to achive it.
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