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maybe i will try this using DC, it supports gated clock constraint.
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For simple reasons already explained by others, if you can't specify a timing relation between a and b input,
no tool will be able to perform a timing analysis. You have to exepect glitches at c. If c is only clocking a single FF as in your example, there are probably no consequences for your design, otherwise you should be cautious.
As an additional remark: The problems brought on by such designs are typically more serious with rare timing violation events. You don't see them in a test, but the system reveals unreliable in operation at customer site.
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