Forum Discussion

Honored Contributor

17 years ago

how to constraint the gated clock in the Timequest？

i need to use gated clock in my design, and like following: module prac ( a, b, rst_n, out ); input a; input b; input rst_n; ...

Honored Contributor

17 years ago

--- Quote Start ---

what are the properties of a and b? are they both masked clocks or one is clock and the other - masking signal?

do you intend c to be edge aligned with a/b?

--- Quote End ---

a and b are both not clock, they are the signals changed between 0 and 1,

the relationship between a and b are uncertain。

the FAQ of altera say i can use"generated clock"command to constraint the output of "and" gate,but i still didn't know how to do this.