Contributor
ContributorHi sstrell
Thank you, sstrell, very much.
Unfortunately, the design I get which is designed by RD use digital divider to divide the Clock_a to the Clock_a1 and the Clock_a2.
(Designer don't use the coding style of the clock enable to design the design because the design style is ASIC.
(And Unfortunately, I can't modify the design.
So, Should I still don't use the "create_generated_clock" command to create Clock_a1 and Clock_a2?
If I don't create Clock_a1 and Clock_a2, Quartus will report some node that "no clocks feeds this register's clock port".
Super ContributorI don't understand. So are Clock_a1 and Clock_a2 identical to Clock_a or are they different? You say "use digital divider to divide" so I don't know if you mean just splitting one source clock into two or if this is like a divide frequency by 2 or something. What are the frequencies of all 3 clocks?
If you can't modify the design, I would just turn off Auto Global for Clock_a1 and Clock_a2. You would still need the generated clock constraints, but they are not complete. They should be like:
create_generated_clock -name Clock_a1 -source Clock_a -multiply_by 1 (or -divide_by if the frequency is divided)
create_generated_clock -name Clock_a2 -source Clock_a -multiply_by 1
ContributorHi sstrell
Sorry that ambiguity. The clocks structure and constraint are as follows.
Clock_a -------------------------------------> Clock_a for IP1
|
---clock divider (Clock_a / 2)--> Clock_a1 for IP2
|
---clock divider (Clock_a / 4)--> Clock_a2 for IP3
creat_clock -name Clock_a [get_ports Clock_a ]
create_generated_clock -name Clock_a1 -source Clock_a -divide_by 2
create_generated_clock -name Clock_a2 -source Clock_a -divide_by 4
As you said, maybe turning off Auto Global is the best choice.
Thank you very, very much.
