how to constrain timing between FPGAs?

I completely agree that I/Os should be constrained with set_input_delay and set_output_delay constraints, which requires an understanding of the external interfaces. My point was that if you constrain both interfaces this way (and choose values for the first FPGA that are slightly larger then the values from report_datasheet), and use these values instead of the ones directly from report_datasheet, the when you make a change to one FPGA, you only have to check timing on the FPGA that you modified, not both.