how to constrain timing between FPGAs?

Jimbo,

Thank you for the answers. I think I have pretty much got it going with both FPGAs meeting setup and hold now. I am happy to hear that the reported tCO is a maximum, as that is the assumption I was operating under.

As to your point# 2, I did use the datasheet numbers from each FPGA to constrain the other. This is because TimeQuests preferred method of constraints involves describing the delays, tCO's, and tSU's outside of the device being constrained. Apparently I can use Timequest to constrain tCO and tSU directly but the guides discourage it. Doing it with the "preferred" constraint technique actually worked out pretty well, after some iterations, the little setup slack I had was evenly split across each FPGA. Maybe I got lucky. As you mention, I just now need to remember to check timing on both FPGAs if anything changes.