how to constrain timing between FPGAs?

1. Yes, the reported tCO is a maximum.

2. One FPGA does not know about the other. I would look at Report Datasheet and see what you get with one FPGA, and then constrain the I/O (with set_input_delay and set_output_delay constraints) to meet the values reported in the datasheet. Then use the constrained numbers (not the datasheet numbers) from the first FPGA to constrain the second FPGA. Now if anything changes, you just have check for failing paths in both FPGAs using TimeQuest and you won't have to iterate with Report Datasheet.