Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

how to constrain timing between FPGAs?

Hi, I have two FPGAs which are each clocked by the same system clock. One FPGA provides a data signal to the other. I want to make sure I am meeting timing. If the source FPGA were a n...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

OK, that makes sense. Perhaps I was over-thinking the problem. Thanks also for the links - it has been long enough since I've seen the "best practices" doc that I forgot about it's existence. It looks useful, along with the super useful wiki user guide.

-Martin