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Altera_Forum
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14 years ago

how to constrain timing between FPGAs?

Hi, I have two FPGAs which are each clocked by the same system clock. One FPGA provides a data signal to the other. I want to make sure I am meeting timing. If the source FPGA were a n...
Altera_Forum's avatar
Altera_Forum
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14 years ago

Yes, this definitely helps, thank you.

I guess what this means is that, in the future, if one of the FPGAs gets re-built, then I will need to run the report_datasheet and recheck the timing on the other FPGA to be sure all is still OK.

Perhaps another approach is to use the set_max_delay and the set_min_delay constraints to put limits on either the Tco/Tco_min or Tsu/Th of the design to help flag an issue during future re-builds. Does this make sense?

Martin