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Altera_Forum
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13 years ago

how to constrain my output port

hi Alt-Gurus: I am constraining my output port say 'foo' in the usual way set_output_delay –clock clk_A –max 3 [get_ports “foo”] Now this port is driven by a register which is clo...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

What I'm saying is that it's perfectly possible to apply a multicycle exception to an output path, between the output FF inside the FPGA and the virtual FF outside the FPGA.