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Altera_Forum
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13 years ago

how to constrain my output port

hi Alt-Gurus: I am constraining my output port say 'foo' in the usual way set_output_delay –clock clk_A –max 3 [get_ports “foo”] Now this port is driven by a register which is clo...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

hi,

CLK_B is only driving the enable of the flip flop.

Are you suggesting that I do set_output_delay to CLK_A and then

a set_multicycle_path between CLK_B and CLK_A?

Since the external register is virtual (i.e. not part of what sta will see)

will this technique work? i.e. I can't do [get_fanouts CLK_A] and expect to see

the external register. In that case how do I set multicycle exception from CLK_B to

this FF?