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Altera_Forum
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13 years ago

how to constrain my output port

hi Alt-Gurus: I am constraining my output port say 'foo' in the usual way set_output_delay –clock clk_A –max 3 [get_ports “foo”] Now this port is driven by a register which is clo...
Altera_Forum's avatar
Altera_Forum
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13 years ago

Didn't quite get the role of clk_B.

Does it drive the output register's clock pin, or is it just used as a clock enable?

If the first, then you need simply to constraint clk_B as a generated clock.

If the later, you can add a multi-path exception.