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Altera_Forum
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15 years ago

How to constrain a source-synchronous desing?

Hi All, I am having problems setting up my sdc constraints for a source-synchronous interface that i have. The design is described as follows. --- The FPGA provide a reference clk(125Mhz) to a...
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Altera_Forum
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15 years ago

Rysc and Kaz,

I'm very grateful to you for your help.

I think I have got the result that I wanted.

Thanks.

Harris