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Altera_Forum
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15 years ago

How to constrain a source-synchronous desing?

Hi All, I am having problems setting up my sdc constraints for a source-synchronous interface that i have. The design is described as follows. --- The FPGA provide a reference clk(125Mhz) to a...
Altera_Forum's avatar
Altera_Forum
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15 years ago

Harris and Rysc :

Using Harris mini-project I did some work on TimeQuest with regard to actual implementation of set_output_delay figures and realised that the equations are correct directly for tSU/tH but not for tCO.

The tCO is computed indirectly from tSU/tH as entered in the equations mentioned in this thread.

Thus the final example that I posted its link is misleading or out of date or badly worded.

Regarding skew: I found lowest data skew when I set all ten output registers to fast io