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Altera_Forum
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15 years ago

How to constrain a source-synchronous desing?

Hi All, I am having problems setting up my sdc constraints for a source-synchronous interface that i have. The design is described as follows. --- The FPGA provide a reference clk(125Mhz) to a...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Either figure has a cloud of delay.

The statement itself is saying about set_output_delay:An output delay constraint on the data_out port, relative to the generated clock on the clk_out port.

I am not sure about reference pin issues but I don't see any reason to use it just to help remove one statement.