How to constrain a source-synchronous desing?

Do you mean, "In the circuit in Figure 2, the latency from the clk_in port to the clk_out port is included by the -reference_pin option"? It's basically saying the Tco to the -reference_pin is used, but the set_output_delay is still describing the delays outside the FPGA, and is not a directly replacement of Tco to the output. Only the -reference_pin option does this. This is another reason I don't like -reference_pin in that it's confusing. Does it include PLL phase-shifts or not? (I really don't know, but a generated clock will).