How to constrain a source-synchronous desing?

I don't see where in the example it says set_output_delay is the same thing as the traditional Tco? If it did say that, it's certainly wrong. The output delay is external delay to an external register, clocked by -clock. I don't even think of set_output_delay and set_input_delay as "constraints". They describe a circuit outside the FPGA. Once that circuit is drawn, we can determine the setup/hold relationships between the launch and latch clocks, the delays outside the FPGA, and finally the delays inside the FPGA to determine if it met timing.

(And I don't like "-reference_pin". It's easy enough to put a generated clock assignment on the output port being referenced, which allows the user to do many things with that generated clock. The -reference_pin can only be used in one manner.)