How to constrain a source-synchronous desing?

We must think of the system centric approach i.e. we need to get timing right for external device. The entry of max/min delay conveys that info to TQ.

Regarding skew: first notice that altera examples in their resource centre are actually targeting skew at FPGA boundary i.e. fpga as a chip and not in any system which is of no use to you and probably to anybody unless you want to sell your fpga on its own.

To control skew within the sytem centric approach, you must first not violate external device but may be you need to exagerate the tSU/tH in order to minimise that wide valid window entered with honest figures of device.