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Altera_Forum
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15 years ago

How to constrain a source-synchronous desing?

Hi All, I am having problems setting up my sdc constraints for a source-synchronous interface that i have. The design is described as follows. --- The FPGA provide a reference clk(125Mhz) to a...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

My design is source-synchronous. According to Altera's input&output delay calculating method, the output -max should be Tsu.

The output -min should be -Th. How to deal with the skew?

I think I can not understand the concept of the data valid window correctly.

I upload a mini version of my project. This mini version have the same problem to my project.

Would you please take a look on this version.

Thanks

Harris