Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

How to constrain a source-synchronous desing?

Hi All, I am having problems setting up my sdc constraints for a source-synchronous interface that i have. The design is described as follows. --- The FPGA provide a reference clk(125Mhz) to a...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

I believe by your words "external delay" you meant (set output delay figures) .

I don't see anything wrong with the output constraints of -.2 & 2.0 instead of -.2 & 1.2 since the valid window is further narrowed to lower the skew.

What I explained was my personal understanding of skew relation to the valid window. The valid window is the primary requirement and skew comes secondary as a subset of that window.